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VES1820X
SINGLE CHIP DVB-C CHANNEL RECEIVER
FEATURES
* 16/32/64/128/256 QAM demodulator (DVB-C compatible : ETS 300-429). * On chip 9-bit ADC. * On chip PLL for crystal frequency multiplication. * Digital down conversion. * Half Nyquist filters (roll off = 15 %). * Automatic gain control PWM output (AGC). * Symbol timing recovery, with programmable second order loop filter. * Variable symbol rate capability from SACLK/64 to SACLK/4 (SACLK max = 36 MHz) * Programmable anti-aliasing filters. * Full digital carrier recovery loop. * Carrier acquisition range up to 8 % of symbol rate. * Integrated adaptative equalizer (Linear Transversal Equalizer or Decision Feedback Equalizer). * On chip FEC decoder (Deinterleaver & RS decoder), full DVB-C compliant. * DVB compatible differential decoding and mapping. * Parallel or serial transport stream interface. * I2C bus interface, for easy control. * CMOS 0.35m technology.
APPLICATIONS
* * * * * DVB-C fully compatible. Digital data transmission using QAM modulations. Cable demodulation. Cable modems MMDS (ETS 300-429).
DESCRIPTION
The VES1820X is a single chip channel receiver for 16, 32, 64, 128 and 256-QAM modulated signals. The device interfaces directly to the IF signal, which is sampled by a 9-bit AD converter. The VES1820X performs the clock and the carrier recovery functions. The digital loop filters for both clock and carrier recovery are programmable in order to optimize their characteristics according to the current application. After base band conversion, equalization filters are used for echo cancellation in cable applications. These filters are configured as Tspaced transversal equalizer or DFE equalizer, so that the system performance can be optimized according to the network characteristics. A proprietary equalization algorithm, independent of carrier offset, is achieved in order to assist carrier recovery. Then a decision directed algorithm takes place, to achieve final equalization convergence. The VES1820X implements a FORNEY convolutional deinterleaver of depth 12 blocks and a Reed-Solomon decoder which corrects up to 8 erroneous bytes. The deinterleaver and the RS decoder are automatically synchronized thanks to the frame synchronization algorithm which uses the MPEG2 sync byte. Finally descrambling according to DVB-C standard, is achieved at the Reed Solomon output. This device is controlled via an I2C bus. Designed in 0.35 m CMOS technology and housed in a 100 pin MQFP package, the VES1820X operates over the commercial temperature range.
comatlas S.A., 30 rue du Chene Germain, BP 814, 35518 CESSON-SEVIGNE Cedex, FRANCE Phone : +33 (0)2 99 27 55 55, Fax : +33 (0)2 99 27 55 27 , Internet: www.comatlas.fr / VES 1820X rev 2.0 / Mar 99
CAUTION
This document is preliminary and is subject to change. Contact a comatlas representative to determine if this is the current information on this device.
The information contained in this document has been carefully checked and is believed to be reliable. However, comatlas makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon, it. comatlas does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark, copyright, mask work right or other rights of third parties, and no patent or other license is implied hereby. This document does not in any way extend comatlas warranty on any product beyond that set forth in its standard terms and conditions of sale. comatlas reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice. LIFE SUPPORT APPLICATIONS : comatlas products are not intended for use as critical components in life support appliances, devices, or systems in which the failure of a comatlas product to perform could be expected to result in personal injury.
comatlas reserves the right to make any change at anytime without notice.
VES 1820X rev 2.0 / Mar 99 / p2
FIGURE 1 : FUNCTIONAL BLOCK DIAGRAM
CLOCK RECOVERY NCO
AGC
8
PWM
TO AGC
IF
9 ADC
BASE-BAND CONVERSION
FILTERS BANK
EQUALIZER
CARRIER RECOVERY
OUTPUT INTERFACE
SACLK
XIN
PLL
R. S. DE-INTERLEAVER DECODER DE-SCRAMBLER
DO OCLK DEN
SDA
2 IC INTERFACE
SCL
comatlas reserves the right to make any change at anytime without notice.
VES 1820X rev 2.0 / Mar 99 / p3
TABLE 1 : ABSOLUTE MAXIMUM RATINGS
Parameter Ambient operating temperature : Ta DC supply voltage DC Input voltage DC Input Current Lead Temperature Junction Temperature Min 0 - 0.5 - 0.5 Max 70 + 4.1 VDD + 0.5 20 +300 +150 Unit C V V mA C C
Stresses above the absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
TABLE 2 : RECOMMENDED OPERATING CONDITIONS
Symbol VDD VCC Ta VIH
1
Parameter Digital supply voltage 5V supply Operating temperature High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Supply current Input capacitance Output capacitance Analog supply voltage Positive analog input Negative analog input
Min 3.14 4.75 0 2 -0.5 VDD -0.1 2.4
Typ 3.3 5
Max 3.46 5.25 70 VCC + 0.3 0.8
Unit V V C V V V
Notes 3.3V 5% pin 17 Ambient temperature TTL input TTL input @ IOH = -0.8 mA @ IOH = + 2mA @ IOL = 0.8 mA @ IOL = + 2mA @XIN = 57.84Mhz Symbol Rate =6Mbd
VIL VOH VOL IDD CIN COUT VD2, VD3, VD4 VIP VIM
2
2
0.1 0.4 200 15 15 3.14 3.3 0.5 -0.5 3.46
V mA pF pF V V V
3.3V 5%
1 2
All inputs are 5V tolerant IOH, IOL = 4mA only for pins SACLK, OCLK, SDA, CTRL1, CTRL2, IT
comatlas reserves the right to make any change at anytime without notice.
VES 1820X rev 2.0 / Mar 99 / p4
FUNCTIONAL DESCRIPTION
1/2 ADC The VES1820X implements a 9-bit analog to digital converter. No external voltage references are required to use the ADC. PLL The VES1820X implements a PLL used as clock multiplier by 1, 2, 3, 4, 5, 6, 7 or 8, so that the crystal can be low frequency (fundamental tone). DOWN CONVERTER AND NYQUIST FILTERS The digital down converter performs the down conversion of the bandpass input signal into the 2 classical quadrature I & Q channels. Then these two signals are passed through anti-alias filters and through a half Nyquist filter having a fixed roll-off of 0.15. The digital filter gives a stop band attenuation of more than 40 dB. EQUALIZER After Nyquist filtering, the signal is fed to an equalization filter, for echo cancellation. This equalizer can be configured as either a transversal Equalizer or a decision feedback equalizer. The following table shows some
-4
1/2
1/2
1/2
echos configuration that the VES1820X corrects with an equivalent degradation of less than 1dB @ BER = 10 . DELAY (nS) 50 150 and 800 1600 AMPLITUDE (dB) -10 -12 and -20 -20 PHASE worst worst worst
1/2 CARRIER RECOVERY The carrier synchronizer implements a fully digital algorithm allowing to recover carrier frequency offsets up to 8 % symbol rate. A phase error detector followed by a programmable second order loop filter provides an estimation of the carrier phase, to compensate the input carrier frequency offset. 1/2 CLOCK RECOVERY A timing error detector implements an application of Gardner algorithm for digital clock recovery. The resulting error is fed to a programmable second order loop filter, which provides a 8-bit command to the NCO block. This one allows to determine the right sampling time instant of the input signal. 1/2 AUTOMATIC GAIN CONTROL An estimation of input signal magnitude is performed and compared to a threshold value which is programmable via the microcontroller interface. The resulting error is then filtered to produce an 10-bit command which is then PWM encoded and provided on pin VAGC. The PWM signal can be passed through a single RC filter to control the input gain amplifier. 1/2 OUTPUT INTERFACE After carrier recovery, the demodulated output symbol must be decoded according to the constellation diagram given by DVB standard for 16, 32, 64, 128 and 256 QAM. The resulting symbols are then differentially decoded (DVB compliant) and serially provided to the FEC part. 1/2 BLOCK SYNCHRONIZATION At demodulator output, the length of some error bursts may exceed that which can be reliably corrected by the Reed-Solomon decoder. The implemented de-interleaving is a convolutional one (Forney) of depth 12. The first operation consists in synchronizing the de-interleaver. This is accomplished by detecting consecutive MPEG2 sync words (or sync ) which are present as the first byte of each packet.
comatlas reserves the right to make any change at anytime without notice.
VES 1820X rev 2.0 / Mar 99 / p5
Next, the RAM memory associated with the deinterleaver fills up and the first deinterleaved bytes are provided to the input of the Reed-Solomon decoder. The state machine of the de-interleaver goes to the control phase which counts consecutive missed MPEG2 sync words (or sync ) before declaring the system desynchronized and going back to the synchronization phase. and are programmable through the I2C interface. When the inverted sync word is detected at the input of the de-interleaver, the bytes provided to the ReedSolomon decoder are inverted at the output of the deinterleaver. 1/2 REED-SOLOMON DECODER The Reed-Solomon decoder decodes the symbol stream from the de-interleaver according to the (204, 188) shortened Reed-Solomon code. Synchronization to Reed-Solomon code is defined over the finite Galois field GF 8 (2 ). The field generator polynomial is given by :
G(x) =
(x +
i= 0
15
i
)
This Reed-Solomon decoder corrects up to eight erroneous symbols in each block. When the correction capability of the decoder is exceeded, the block is not changed and is provided as it has been entered. In this case the flag UNCOR is set and the MSB of the second byte in the MPEG2 frame is forced to one (error indicator). The correction capability of the RS decoder can be inhibited. 1/2 DESCRAMBLER In order to comply with energy dispersal requirements of radio transmission regulations and to ensure adequate binary transitions, the MPEG2 frames are scrambled at the encoder side. Dual operation is achieved at the output of the Reed-Solomon decoder using the same scrambler/descrambler. The polynomial for the pseudo
14 15
random binary sequence (PRBS generator is 1 + x + x . The PRBS registers are initialized at the start of every eight transport packets. To provide an initialization signal for the descrambler, the MPEG2 sync byte of the first transport packet is inverted from 47 to B8 . When detected, the descrambler is loaded with the initial sequence
16 16
"100101010000000". The descrambler can be inhibited. 1/2 INTERFACE The VES1820X integrates an I2C interface in slave mode. This I2C interface fulfills the Philips component I2C bus specification.
comatlas reserves the right to make any change at anytime without notice.
VES 1820X rev 2.0 / Mar 99 / p6
INPUT - OUTPUT SIGNAL DESCRIPTION
SYMBOL CLR# PIN NUMBER 27 TYPE I DESCRIPTION The CLR# input is asynchronous and active low, and clears the VES1820X. When CLR# goes low, the circuit immediately enters its RESET mode and normal operation will resume 4 XIN falling edges later after CLR# returned high. The I2C register contents are all initialized to their default values. The minimum width of CLR# at low level is 4 XIN clock periods. XTAL oscillator input pin. Typically a fundamental XTAL oscillator is connected between the XIN and XOUT pins (see typical application on Error! Reference source not found. page Error! Bookmark not defined.). The XTAL frequency MUST be chosen so that the system frequency SYSCLK (= XIN * multiplying factor of the PLL) equals to 1.6 times the tuner output Intermediate Frequency : SYSCLK = 1.6 x IF. XTAL oscillator output pin. Typically a fundamental XTAL oscillator is connected between the XIN and XOUT pins (see typical application Error! Reference source not found. page Error! Bookmark not defined.). Sampling CLocK. This output clock can be fed to an external 9-bit ADC as the sampling clock.SACLK = SYSCLK/2. FI [8:0] is the 9-bit input of the IF signal. FI[8:0] is the output of an external A/D converter. FI[8] is the MSB. When not used, must be tied to ground. PWM encoded output signal for AGC. This signal is typically fed to the AGC amplifier through a single RC network (see typical application Error! Reference source not found. page Error! Bookmark not defined.). The maximum signal frequency on VAGC output is XIN/16. AGC information is refreshed every 1024 symbols. Data Output bus . These 8-bit parallel data are the outputs of the VES1820X after demodulation, de-interleaving, RS decoding and descrambling. When one of the two possible parallel interfaces is selected (Parameter SERINT=0, index 2016) then DO[7:0] is the transport stream output. When the serial interface is selected (Parameter SERINT=1, index 2016) then the serial output is on pin DO[0] (pin 55). Output CLock. OCLK is the output clock for the parallel DO[7:0] outputs. OCLK is internally generated depending on which interface is selected. Data ENable : this output signal is high when there is a valid data on output bus DO[7 :0]. UNCORrectable packet. This output signal is high when the provided packet is uncorrectable (during the 188 bytes of the packet). The uncorrectable packet is not affected by the Reed Solomon decoder, but the MSB of the byte following the sync. byte is forced 1 for the MPEG2 process : Error Flag Indicator (if RSI and IEI are set low in the I2C table). Pulse SYNChro. This output signal goes high when the sync byte (4716) is provided, then it goes low until the next sync byte. If the serial interface is selected, then PSYNC is high only during the first bit of the sync byte (4716). See Error! Reference source not found. page Error! Bookmark not defined.. TESTO [16:0] is 17-bit Test output bus. VES 1820X rev 2.0 / Mar 99 / p7
XIN
2
I
XOUT
3
O
SACLK FI[8:0]
18 5,6,7,8,12, 13,14,15,16 20
O (5V) I
VAGC
O (5V)
DO[7:0]
46,49,50,51 52,53,54,55
O (3.3V)
OCLK
44
O (3.3V) O (3.3V) O (3.3V)
DEN UNCOR
45 42
PSYNC
43
O (3.3V)
TESTO[16:0]
78,77,76,75,74
O
comatlas reserves the right to make any change at anytime without notice.
SYMBOL
IICDIV[1:0]
PIN NUMBER 71,70,69,68,67 64,63,62,61,60 57,56 21,22
TYPE (3.3V)
DESCRIPTION
I
SADDR[1:0]
23,24
I
SDA
26
I/O (5V) I
SCL
25
TEST TRST
19 35
I I
TDO TCK
37 33
O (5V) I
TDI
34
I
TMS
36
I
CTRL1
31
I/O (5V)
CTRL2
32
O (5V)
IT
38
O (5V)
FEL
39
O (5V)
VIP
92
I
VIM
91
I
IICDIV[1:0] allow to select the frequency of the I2C internal system clock, depending on the crystal frequency. Internal I2C clock is a IICDIV and must be between 6 and 20 MHz. division of XIN by 2 SADDR[1:0] are the 2 LSBs of the I2C address of the VES1820X. The MSBs are internally set to 00010. Therefore the complete I2C address of the VES1820X is (MSB to LSB) : 0, 0, 0, 1, 0, SADDR[1], SADDR[0]. SDA is a bidirectional signal. It is the serial input/output of the I2C internal block. A pull-up resistor (typically 4.7 k) must be connected between SDA and VDD for proper operation (Open Drain output). I2C clock input. SCL should nominally be a square wave with a maximum frequency of 400KHz. SCL is generated by the system I2C master. Test input pin. For normal operation of the VES1820X, TEST must be grounded. Test ReSeT. This active low input signal is used to reset the TAP controller when in boundary scan mode. In normal mode of operation TRST must be set low. Test Data Out. This is the serial Test output pin used in boundary scan mode. Serial Data are provided on the falling edge of TCK. Test ClocK : an independant clock used to drive the TAP controller when in boundary scan mode. In normal mode of operation, TCK must be grounded. Test Data In. The serial input for Test data and instruction when in boundary scan mode. In normal mode of operation, TDI must be set to GND. Test Mode Select. This input signal provides the logic levels needed to change the TAP controller from state to state. In normal mode of operation, TMS must be set to VDD. CTRL1 is equivalent to SDA I/O of VES1820X but can be tri-stated by I2C programmation. It is actually the output of a switch controlled by parameter BYPIIC of register TEST (index 0F16). CTRL1 is open drain output, and therefore requires an external pull up resistor. CTRL2 can be configured to be a control line output or to output SCL input. This is controlled by parameter BYPIIC of register TEST (index 0F16). CTRL2 is an open drain output and therefore requires an external pull up resistor. InTerrupt line. This active low output interrupt line can be configured by the I2C interface. See registers ITsel (index 3216) and ITstat (index 3316). IT is an open drain output and therefore requires an external pull up resistor. By default FEL is a front-end lock indicator. In this case FEL is an open drain output and therefore requires an external pull up resistor. But FEL can also be configured to output a PWM signal, which value can be programmed through the I2C interface (see register PWMREF, index 3416). Positive input to the A/D converter. This pin is DC biased to halfsupply through an internal resistor divider (2 x 10k resistors). In order to remain in the range of the ADC, the voltage difference between pins VIP and VIM should be between -0.5 and 0.5 volts. Negative input to the A/D converter. This pin is DC biased to halfVES 1820X rev 2.0 / Mar 99 / p8
comatlas reserves the right to make any change at anytime without notice.
SYMBOL
PIN NUMBER
TYPE
CMCAP
85
I
RBIAS
82
I
VREF
88
O
VREFP
87
O
VREFM
86
O
CMO
84
O
CMI
83
O
VD1 VS1 VD2 VS2 VD3 VS3 VD4 DVCC DGND PLLGND PLLVCC PPLUS
81 80 94 93 89 90 95 96 97 98 99 100
I I I I I I I I I I I I
DESCRIPTION supply through an internal resistor divider (2 x 10k resistors). In order to remain in the range of the ADC, the voltage difference between pins VIP and VIM should be between -0.5 and 0.5 volts. This pin is connected to a tap point on an internal resistor divider used to create CMO and CMI. An external capacitor of value 0.1f should be connected between this point and ground to provide good power supply rejection from the positive supply at higher frequencies. An external resistor of value 3.3k should be connected between this pin and ground to provide good accurate bias currents for the analog circuits on the ADC. This is the output of an on-chip resistor divider. An external capacitor of value 0.1f should be connected between this point and ground to provide good power supply rejection from the positive supply at higher frequencies. Reference voltages VREFP and VREFM are derived from the voltage on VREF. This is a positive voltage reference for the A/D converter. It is derived from the voltage on pin VREF through an on-chip fully-differential amplifier. The voltage on this pin is nominally equal to CMO + 0.25 volts. This is the negative voltage reference for the A/D converter. It is derived from the voltage on pin VREF through an on-chip fullydifferential amplifier. The voltage on this pin is nominally equal to CMO- 0.25 volts. This pin provides the common-mode out voltage for the analog circuits on the ADC. It is the buffered version of a voltage derived from an on-chip resistor devider, and has a nominal value of 0.5 x VD3. This pin provides the common-mode in voltage for the analog circuits on the ADC. It is the buffered version of a voltage derived from an on-chip resistor devider, and has a nominal value of 0.75 x VD3. Power supply input for the digital switching circuitry (3.3 typ). Ground return for the digital switching circuitry. Power supply input for the analog clock drivers (3.3V typ). Ground return for the analog clock drivers. Power supply input for the analog circuits (3.3V typ). Ground return for analog circuits. Power supply input that connects to an n-well guard ring that surrounds the ADC (3.3V typ). 3.3V supply for the digital section of the PLL. Ground connection for the digital section of the PLL. Ground connection for the analog section of the PLL. 3.3V supply for the analog section of the PLL. P-well bias for the analog section of the PLL. Must be tied to 0V.
comatlas reserves the right to make any change at anytime without notice.
VES 1820X rev 2.0 / Mar 99 / p9
FIGURE 2 : BLOCK DIAGRAM
VDD GND VCC VDi VSi 11 11 4 4
XIN
XOUT
POWER SUPPLIES
SACLK VAGC CTRL1 CTRL2 IT
FI[8:0] TEST CLR# VIP VIM
9 INPUTS
VES1820X
OUTPUTS
FEL PSYNC UNCOR DEN OCLK DO[7:0]
8 IICDIV[1:0] INTERFACE TEST 18 TESTO[16:0] JTAG
3 SADDR[1:0] SCL SDA
4 TDO
FIGURE 3 : PIN DIAGRAM
PLLGND PLLVCC CMCAP VREFM PPLUS
100
VREFP VREF VD3 VS3
RBIAS CMI CMO
95
90
85
VDD XIN XOUT GND FI[8] FI[7] FI[6] FI[5] VDD GND GND FI[4] FI[3] FI[2] FI[1] FI[0] VCC(5V) SACLK TEST VAGC IICDIV[1] IICDIV[0] SADDR[1] SADDR[0] SCL SDA CLR# VDD GND GND
81
DVCC DGND
VS2 VD2 VD4
VIM
VD1
VIP
1
80
VS1 VS4 TESTO[16] TESTO[15] TESTO[14]
5 75
TESTO[13] TESTO[12] GND VDD TESTO[11]
10 70
TESTO[10] TESTO[9] TESTO[8] TESTO[7]
15
VES1820X
65
GND VDD TESTO[6] TESTO[5] TESTO[4] TESTO[3]
20 60
TESTO[2] GND VDD TESTO[1]
25 55
TESTO[0] DO[0] DO[1] DO[2] DO[3] DO[4]
30
31 35 40 45 50
51
comatlas reserves the right to make any change at anytime without notice.
CTRL2 CTRL1
TCK
TRST TDI
TDO TMS
FEL IT
UNCOR GND VDD
DEN OCLK PSYNC
DO[7]
DO[5] DO[6]
GND VDD
VES 1820X rev 2.0 / Mar 99 / p10
TABLE 3 : PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Pin Name VDD XIN XOUT GND FI[8] FI[7] FI[6] FI[5] VDD GND GND FI[4] FI[3] FI[2] FI[1] FI[0] VCC SACLK TEST VAGC IICDIV[1] IICDIV[1] SADDR[1] SADDR[0] SCL SDA CLR# VDD GND GND CTRL1 CTRL2 TCK Direction I O I I I I I I I I I O I O I I I I I I/O I I/O OD I Pin 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Pin Name TDI TRST TMS TDO IT FEL VDD GND UNCOR PSYNC OCLK DEN DO[7] VDD GND DO[6] DO[5] DO[4] DO[3] DO[2] DO[1] DO[0] TESTO[0] TESTO[1] VDD GND TESTO[2] TESTO[3] TESTO[4] TESTO[5] TESTO[6] VDD GND Direction I I I OD OD OD O O O O O O O O O O O O O O O O O O O Pin Pin Name Direction 67 TESTO[7] O 68 TESTO[8] O 69 TESTO[9] O 70 TESTO[10] O 71 TESTO[11] O 72 VDD 73 GND 74 TESTO[12] O 75 TESTO[13] O 76 TESTO[14] O 77 TESTO[15] O 78 TESTO[16] O 79 VS4 80 VS1 81 VD1 82 RBIAS I 83 CMI O 84 CMO O 85 CMCAP I 86 VREFM O 87 VREFP O 88 VREF O 89 VD3 90 VS3 91 VIM I 92 VIP I 93 VS2 94 VD2 95 VD4 96 DVCC 97 DGND 98 PLLGND 99 PLLVCC 100 PPLUS -
Notes : 1.All inputs (I) are TTL, 5V tolerant inputs 2.OD are Open Drain 5V outputs, so they must be connected to a pull-up resistor to either VDD or VCC
comatlas reserves the right to make any change at anytime without notice.
VES 1820X rev 2.0 / Mar 99 / p11
comatlas S.A., 30 rue du Chene Germain, BP 814, 35518 CESSON-SEVIGNE Cedex, FRANCE Phone : +33 (0)2 99 27 55 55, Fax : +33 (0)2 99 27 55 27 , Internet: www.comatlas.fr comatlas reserves the right to make any change at anytime without notice. comatlas reserves the right to make any change at anytime without notice. VES 1820X rev 2.0 / Mar 99 / p12

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